Instruction-Based Sampling (IBS) is a performance monitoring technique that provides precise information about AMD64 instruction fetch behavior and about the execution of operations that are issued from AMD64 instructions. This information can be used to analyze and improve the performance of programs executing on AMD “Barcelona” processors.
IBS provides four important advantages over conventional performance counter sampling:
- Hardware events are attributed precisely to the instructions that cause the events. Conventional performance counter sampling is not precise making it difficult, if not impossible, to attribute events to specific instructions. This limits the ability to pin-point performance issues at the instruction and source code levels.
- A wide range of events are monitored and collected with each IBS sample. Either multiple sampling runs or counter multiplexing must be used to collect the same range of information with conventional performance counter sampling.
- The virtual and physical addresses of load/store operands are collected. Profiling tools can use this information to associate specific data structures with x86 instructions performing load/store operations.
- Latency is measured for key performance parameters such as data cache miss latency.
The precision afforded by IBS also enables automated optimization techniques (e.g., profile-directed optimization) which require detailed, precise information about instruction-level program behavior.
More information will be forthcoming in an appendix to be added to the Software Optimization Guide for AMD Family 10h Processors.
IBS support is included in the latest beta release of AMD CodeAnalyst, version 2.7.4.
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