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“Barcelona” Processor Feature: CPUID

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To use or not to use CPUID, that is the question. CPUID is an instruction that tells you what features of a processor are supported. This instruction definitely has a time and place to be used and not to be used. For general optimizations, CPUID can be a crucial step that ensures compatibility in your code, but for multithreaded code, you’re much better off using OS methods to detect the processor topology.

As newer processors enter the market, they come loaded with new software visible features. Take SSE4a, for example, a new set of SIMD instructions included in AMD “Barcelona” processors, but not included in any previous AMD processors. If you are doing optimizations and want to use those instructions, it’s highly recommended to use CPUID to first determine if the processor supports SSE4a, and then take the appropriate code path depending on the result of the operation. Adding this crucial step ensures that your code doesn’t break if it is run on an older processor without SSE4a instructions. Check out Appendix E of the AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions for details on how to use CPUID properly to detect various features.

When it comes to parallel programming, processor topology is key to writing optimized multithreaded code. Things like cache architecture (size, levels, shared or not shared, etc.), NUMA rules, and number of cores are some of the main things that could affect your code. The best method for determining processor topology is to use the methods provided by the operating system. For example, in Windows, the API call GetLogicalProcessorInformation allows an application to learn about the machine’s configuration, including multi-core and NUMA. Relying on operating system APIs to enumerate topology information is not only easier from a coding standpoint, but in a virtualized environment not all processors or nodes may be available for use — something that CPUID may not properly reflect.


This post is the opinion of the author and may not represent AMD’s positions, strategies or opinions. Links to third party sites and references to third party trademarks are provided for convenience and illustrative purposes only. Unless explicitly stated, AMD is not responsible for the contents of such links, and no third party endorsement of AMD or any of its products is implied.


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